View ML145146-6P_7556036.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.lansdale.com page 1 of 12 issue 0 ml145146 4bit data bus input pll frequency synthesizer legacy device: motorola mc145146-2 the ml145146 is programmed by a 4?it input, with strobe and address lines. the device features consist of a reference oscillator, 12?it programmable reference divider, digital phase detector, 10?it programmable divide?y? counter, 7?it divide?y? counter, and the necessary latch circuitry for accepting the 4?it input data. ? operating temperature range: t a ?40 to +85? ? low power consumption through the use of cmos technology ? 3.0 to 9.0 v supply range ? programmable reference divider for values between 3 and 4095 ? dual?odulus 4?it data bus programming ? n range = 3 to 1023, a range= 0 to 127 ? ?inearized?digital phase detector enhances transfer function linearity ? two error signal options: single?nded (three?tate) double?nded p dip 20 = rp plastic dip case 738 sog 20 w = -6p sog package case 751d 20 1 20 1 cross reference/ordering information motorola p dip 20 mc145146p2 ml145146rp sog 20w mc145146dw2 ML145146-6P lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin assignment v dd v ss f in d0 d1 a1 a0 osc out osc in pd out 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 v r f r d3 d2 a2 st ld f v mc interfaces with dual?odulus prescalers block diagram modulus control (mc) 7?it a counter control logic pd out ld lock detect phase detector b phase detector a st a0 a1 a2 d3 d2 d1 d0 12?it r counter latches latch control circuitry 10?it n counter osc in osc out f in l5 l6 l7 l2 l3 l4 l0 l1 f r v r f v
lansdale semiconductor, inc. ml145146 www.lansdale.com page 2 of 12 issue 0
lansdale semiconductor, inc. ml145146 www.lansdale.com page 3 of 12 issue 0
lansdale semiconductor, inc. ml145146 www.lansdale.com page 4 of 12 issue 0
lansdale semiconductor, inc. ml145146 www.lansdale.com page 5 of 12 issue 0
lansdale semiconductor, inc. ml145146 www.lansdale.com page 6 of 12 issue 0 pin descriptions input pins d0 - d3 data inputs (pins 2, 1, 20, 19) information at these inputs is transferred to the internal latches when the st input is in the high state. d3 (pin 19) is the most significant bit. f in frequency input (pin 3) input to ? portion of synthesizer f in is typically derived from loop vco and is ac coupled into pin 3. for larger amplitude signals (standard cmos ?logic levels) dc coupling may be used. osc in /osc out reference oscillator input/output (pins 7 and 8) these pins form an on?hip reference oscillator when con- nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be con- nected from osc in to ground and osc out to ground. osc in may also serve as input for an externally?enerated reference signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos?ogic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . a0 - a2 address inputs (pins 9, 10, 11) a0, a1 and a2 are used to define which latch receives the information on the data input lines. the addresses refer to the following latches. st strobe transfer (pin 12) the rising edge of strobe transfers data into the addressed latch. the falling edge of strobe latches data into the latch. this pin should normally be held low to avoid loading latches with invalid data. output pins pdout single?nded phase detector output (pin 5) three?tate output of phase detector for use as loop error signal. frequency f v >f r or f v leading: negative pulses frequency f v lansdale semiconductor, inc. ml145146 www.lansdale.com page 7 of 12 issue 0
lansdale semiconductor, inc. ml145146 www.lansdale.com page 8 of 12 issue 0 design considerations crystal oscillator considerations the following options may be considered to provide a refer- ence frequency to motorolas cmos frequency synthesizers. the most desirable is discussed first. use of a hybrid crystal oscillator commercially available temperature?ompensated crystal oscillators (tcxos) or crystal?ontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of sinking and sourcing 50 a at cmos logic levels may be direct or dc coupled to osc in . in general, the highest frequency capability is obtained utilizing a direct coupled square wave having a rail?o?ail (v dd to v ss ) voltage swing. if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling of osc in may be used. osc out , an unbuffered output, should be left floating. for additional information about tcxos and data clock oscillators, please consult the latest version of the eem electronic engineers master catalog , the gold book , or simi- lar publications. design an off?hip reference the user may design and off?hip crystal oscillator using ics specifically developed for crystal oscillator applications, such as the ml12061 mecl device. the reference signal from the mecl device is ac coupled to osc in . for large ampli- tude signals (standard cmos logic levels), dc coupling is used. osc out , an unbuffered output, should be left floating. in general, the highest frequency capability is obtained with a direct?oupled square wave having rail?o?ail voltage swing. use of the on?hip oscillator circuitry the on?hip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 8. for v dd = 5.0 v, the crystal should be specified for a load- ing capacitance. c l , which does not exceed 32 pf for frequen- cies to approximately 8.0 mhz, 20 pf for frequencies in the area of 8.0 to 15 mhz, and 10 pf for higher frequencies. these are guidelines that provide a reasonable compromise between ic capacitance, drive capability, swamping variations stray in ic input/output capacitance, and realistic c l values. the shunt load capacitance, c l , presented across the crystal can be esti- mated to be: where c in = 5.0pf (see figure 9) c out = 6.0pf (see figure 9) c a = 1.0pf (see figure 9) c o = the crystals holder capacitance (see figure 10) c1 and c2 = external capacitors (see figure 8) the oscillator can be ?rimmed?on?requency by making a portion or all of c1 variable. the crystal and associated com- ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. in some cases, stray capacitance should be added to the value for c in and c out . power is dissipated in the effective series resistance of the crystal, r e . in figure 10 the drive level specified by the crys- tal manufacturer is the maximum stress that a crystal can with- stand without damaging or excessive shift in frequency. r1 in figure 8 limits the drive level. the use of r1 may not be nec- essary in some cases (i.e. r1 = 0 ohms). to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func- tion of voltage at osc out . (care should be taken to minimize loading.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdrive condition exists. the user should note that the oscillator start?p time is propor- tional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have developed expertise in cmos oscillator design with crystals. discussions with such manufacturers can prove very helpful. see table 1.
lansdale semiconductor, inc. ml145146 www.lansdale.com page 9 of 12 issue 0 recommended reading technical note tn?4 statek corp. technical note tn? statek corp. e. hafner, ?he piezoelectric crystal unit ?definitions and method of measurement? proc. ieee , vol 57, no 2 feb, 1969 d. kemper, l. rosine, ?uartz crystals for frequency control? electro?ecchnology , june 1969 p.j. ottowitz, aguide to crystal selection? electronic design , may 1966 dual?odulus prescaling the technique of dual?odulus prescaling is well estab- lished as a method of acheiving high performance frequency synthesizer operation at high frequencies. basically, the approach allows relatively low?requency programmable coun- ters to be used as high?requency programmable counters with speed capability of several hundred mhz. this is possible without the sacrifice in system resolution and performance that results if a fixed (single?odulus) divider is used for the prescaler. in dual?odulus prescaling, the lower speed counters must be uniquely configured. special control logic is necessary to select the divide value p or p 1 in the prescaler for the required amount of time (see modullus control definition). lansdales dual?odulus frequency synthesizers contain this feature and can be used with a variety of dual?odulus prescalers to allow speed, complexity and cost to be tailored to the system requirements. prescalers having p, p 1 divide val- ues in the range of ?/? to ?28/?29 can be controlled by most lansdale frequency synthesizers. several dual?odulus prescaler approaches suitable for use with the ml145146 are: design guidelines the system total divide value. n total (n t ) will be dictated by the application. i.e., n is the number programmed into the ? counter, a is the number programmed into the ? counter, p and p 1 are the two selectable divide ratios available in the dual?odulus prescalers. to have a range of n t values in sequence, the ? counter is programmed from zero through p 1 for a particu- lar value n in the ? counter. n is then incremented to the n 1, and the ? is sequenced from 0 through p 1 again. there are minimum and maximum values that can be achieved for n t . these values are a function of p and the size of the ? and ? counters. the constraint n a always applies. if a max = p ?1, then n min p ?1. then ntmin = (p 1) p + a or (p 1)p since a is free to assume the value of 0. n tmax ? max ?p + a max to maximize system frequency capability, the dual?odulus prescaler output must go from low to high after each group of p or p ?1 input cycles. the prescaler should divide by p when its modulus control line is high and by p ?1 when the modulus control is low. for the maximum frequency into the prescaler (f vco max), the value used for p must be large enough such that: 1. f vco max divided by p may not exceed the frequency capability of f in (input to the ? and ? counters). 2. the period of f vco divided by p must be greater than the sum of the times: a. propagation delay through the dual modulus prescaler. b. prescaler setup or release time relative to its modulus control signal. c. propagation time from f in to the modulus control output for the frequency synthesizer device. a sometimes useful simplification in the programming code can be achieved by choosing the values for p of 8, 16, 32, or 64. for these cases, the desired value of n t results when n t in binary is used as the program code to the ? and ? coun- ters treated in the following manner: 1. assume the ? counter contains ??bits where 2 a p. 2. always program all higher order ? counter bits above ??to 0 3. assume the ? counter and the ? counter (with all the higher order bits above ??ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the ? counter). the msb of this hypothetical counter is to correspond to the msb of ? and the lsb is to correspond to the lsb of ?. the system divide value, n t , now results when the value of n t in binary is used to program the ?ew?n + a bit counter. by using the two devices, several dual?odulus values are achievable (shown in figure 11). ml12009 ml12011 ml12013 ml12015 ml12016 ml12017 ml12018 ml12032 440 mhz 500 mhz 500 mhz 225 mhz 225 mhz 225 mhz 520 mhz 1.1 ghz ?/? ?/? ?0/?1 ?2/?3 ?0/?1 ?4/?5 ?28/?29 ?4/65 or ?28/129
lansdale semiconductor, inc. ml145146 www.lansdale.com page 10 of 12 issue 0 application the features of the ml145146 permit bus operation with a dedicated wire needed only for the strobe input. in a micro- processor?ontrolled system this strobe input is accessed when the phase lock loop is addressed. the remaining data and address inputs will directly interface to the microproces- sors data and address buses. the device architecture allows the user to establish any integer reference divide value between 3 and 4095. the wide selection of ? values permits a high degree of flexibility in choosing the reference oscillator frequency. as a result the reference oscillator can frequently be chosen to serve multi- ple system functions such as a second local oscillator in a receiver design or a microprocessor system clock. typical applications that take advantage of these ml145146 features including the dual modulus capability are shown in figures 12, 13 and 14. device b device a mc device b device a mc10131 ml12009 ml12011 ml12013 mc10138 mc10154 ?0/?1 ?0/?1 ?0/?1 ?0/?1 or ?2/?3 ?0/?1 ?4/?5 ?0/?1 ?00/?01 ?0/?1 ?28/?29 or note: ml12009, ml12011 and ml12013 are pin equivalent. ml12015, ml12016 and ml12017 are pin equivalent. figure 11. dual modulus values
lansdale semiconductor, inc. ml145146 www.lansdale.com page 11 of 12 issue 0 choice of ref. osc. frequency (on?hip osc. optional) choice of ref. osc. frequency (on?hip osc. optional) } } } } for use with external phase detector (optional) for use with external phase detector (optional) lock detect signal lock detect signal receiver lo. 443.325 443.950 mhz (25 khz steps) 8 osc out mod control pd out f r f in d3 d2 d1 d0 a2 a1 a0 st r v f v ld osc in v dd v ss 7 5 3 17 16 14 6 4 7 8 6 4 19 20 1 2 11 10 9 12 18 15 13 ml145146 mod control pd out f r f in d3 d2 d1 d0 a2 a1 a0 st r v f v ld osc in v dd v ss ml145146 loop filter vco transmitter modulation and 15.7 mhz offset choice of detector error signals ml12034 prescaler transmitter signal 459.025 ?459.650 mhz (25 khz steps) chip select to controller to shared controller bus 19 20 1 2 11 10 9 12 3 14 16 17 5 chip select to controller to shared controller bus notes: 1. reciever i.f = 10.7 mhz, low side injection. 2. duplex operation with 5 mhz receive/transmit separation. 3. f r = 25 khz, + r chosen to correspond with desired reference oscillator frequency. 4. n total = 17,733 to 17,758 = n ?p + a; n = 227, a = 5 to 30 for p = 64. figure 13. synthesizer for uhf mobil radio telephone channels demonstrates use of the ml145146 in microprocessor/microcomputer controlled systems operating to several hundred mhz notes: 1. receiver 1st i.f. = 45 mhz, low side injection; receiver 2nd i.f. = 11.7 mhz, low side injection. 2. duplex operation with 45 mhz receive/transmit separation. 5. only one implementation is shown. various other configurations and dualmodulus prescaling values to 128/129 are possible. 3. f r = 7.5 khz, + r = 1480. 4. n total = n ?32 + a = 27,501 to 28,166: n = 859 to 880; a = 0 to 31. figure 14. 666 channel, computer controlled, mobile radio telephone synthesizer for 800 mhz cellular radio systems osc out x3 receiver 2nd, l.o. 33,300 mhz receiver first l.o. 825.030 844.980 mhz (30 khz steps) loop filter vco x4 x4 transmitter modulation transmitter signal 825.030 844.880 mhz (30 khz steps) choice of detector error signals mc10131 dual f/f ml12011 ?/? prescaler +32/+32 dual modulus prescaler
lansdale semiconductor, inc. ml145146 www.lansdale.com page 12 of 12 issue 0 sog = -6p (mc145146-6p) case 751d-04 -a- -b- p 10 pl 1 1 0 11 20 -t- k c r x 45 m f j 0.25 (0.010) t b ms a s 0.25 (0.010) b mm notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982 2. controlling dimension: millimeter 3. dimensiona and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.00 6 ) per side 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total, in excess of d dimension at maximum material condition. inches dim a b min 12. 6 5 7.40 max 12. 9 5 7. 6 0 min 0.4 99 0.2 9 2 max 0.510 0.2 99 c 2.35 2. 6 5 0.0 9 3 0.104 d 0.35 0.4 9 0.014 0.01 9 f 0.50 0. 9 0 0.020 0.035 g 1.27 b sc 0.050 b sc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.020 0.035 m p 10.05 10.5 6 .03 9 5 0.415 r 0.25 0.75 0.010 0.02 9 millimeters outline dimensions plastic dip (mc145146rp) case 738-03 -a- c k n e seating plane gf d 20 pl 0.25 (0.010) t a mm 0.25 (0.010) t b mm j 20 pl l m -t- 1 1 0 11 20 b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982 2. controlling dimension: inch 3. dimension l to center of lead when formed parallel 4. dimension b does not include mold flash inches dim a b c d e f g j k l m n min 1.010 0.240 0.150 0.015 0.050 b sc 1.27b sc 0.050 0.100 b sc 0.008 0.110 0.300 b sc 7. 6 2 b sc 0.020 max 1.070 .02 6 0 0.180 0.022 0.070 0.015 0.140 0.040 min 25. 66 6 .10 3.81 0.3 9 1.27 2.54 b sc 0.21 2.80 0.51 max 27.17 6 . 6 0 4.57 0.55 1.77 0.38 3.55 1.01 millimeters lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical parameters which may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by the customers technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc.

▲Up To Search▲

Price & Availability of ML145146-6P

	To Download ML145146-6P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .